TI 66AK2E05 custom SoM

Layout view of the 12Layer HDI board

Layout view of the 12Layer HDI board


Ti 66AK2E05 SoM with Zynq BMC

Ti 66AK2E05 SoM with Zynq BMC

Design a compact module for the Texas Instruments 66AK2E05 Processor with memory subsystem, clock sources for the processor cores and high speed serial interfaces. Provide flexible access to GPIOs and debug interfaces.


The Ti 66AK2E05 requires a precisely timed power up , reset and configuration signal sequence in order to reach a functional state. The configuration- or mode-pins are shared with the GPIO pins, which need to be available after power up.

The high speed transceivers (up to 10 Gb) require a low jitter power source, low jitter clock reference and a capable interconnect in order to have adequate link budget on low cost carrier PCBs.


Since the BMC (Board Management Controller) solution of the reference design was not adequate as it relied on a “boat-load” of SPI port expanders, level shifters and an obsolete micro- controller, we decided to implement our own BMC with a Xilinx Zynq. The power-up sequence is implemented as a hybrid design where HW counters in the FPGA fabric provide deterministic action points on a configurable timeline and the processing subsystem implements the I2C based configuration of clock chips and PM bus based Point of Load power management chips. The GPIO pins of the Ti that serve as mode pins during power up, are later multiplexed through the FPGA fabric and made avaliable as GPIO’s on the low speed connector of the module. Since the Zynq provides 200 pins on the FPGA fabric, we could implement a range of additional features that expand the possibilities of the module:

  • The Asynchronous memory interface of the Ti 66AK2E05 was mapped to the Zynq FPGA fabric, this allows for memory mapped peripherals to be implemented in the FPGA. Possible applications are precision timers, additional serial interfaces or security features such as HW encryption. Additional uses can be a serial loader from BMC to boot Flash of the Ti which is also on the asynchronous memory interface.
  • The Debug interface of the Ti was mapped to the FPGA fabric which allows for the implementation of an on-board debugger
  • The FPGA based GPIO pins on the module connector can be utilized as a debug port where a logic analyzer can be attached
  • Spare serial ports of the Ti were connected to the BMC’s serial ports, therefore data can easily be exchanged between the two processor systems. The Ti application can invoke a power cycle, request clock frequency changes or simply enquire about low level system conditions.
  • The 11 high speed clock references are generated by two CDCM6208 clock management chips which are driven by a range of on board and external reference sources.
  • High speed interconnect is provided by 28Gb capable connectors from Samtec.

Skills and Technologies used:

Impedance controlled Layout for fast DDR3 memory and high-speed serial links up to 10 Gb. Software development for BMC, FPGA development for BMC. Linux FSBL adaptations.