KRM meet xilinx AR# 65240

December 2015. All of the KRM-3xxx and KRM-1xxx modules have been verified to meet the criteria for safe power up and power down sequencing as outlined in Xilinx’s AR# 65240.

Posted in News

KRM-1k Preview

July 2015, our latest member of the KRM SoM Product line up is the new KRM1ZQ10; a low-cost, compact 30x70mm SO-DIMM module featuring a Zynq 7010 (or 7020) SoC with 512MB RAM, 2 QSPI Flash memories for configuration, 100 PL IO’s and 38 PS MIOs. The module runs on a single 3V3 Supply and provides up to 1.5A of regulated 1V8 for low power peripherals.

In addition to the full featured version, a reduced feature “micro controller” version with 512kB on chip program memory and 256kB on chip RAM (no external DDRIII) is available for cost sensitive applications that require the speed of an FPGA fabric coupled with the flexibility of a high performance dual core CPU but do not have a large memory footrpint. Example applications are: Motor control, real-time video processing (line buffer based) and high I/O count industrial control.

Pricing starts at € 59.00 for the uP version in large quantities


Posted in News

New Appnote

March 2015, a new application note describing the use of aurora IP blocks in conjuction with KRM project scripts and the KRM3510 subcarrier is available for download in the KRM3510 product section. The appnote illustrates how a designer can quickly achieve 8Gb serial connectivity via optical or elctrical SPF+ links when using a KRM-3Z30 (or higher) module on the KRM3500 series carriers.

Posted in Featured, News

KR at Embedded World 2015

February 24th through 26th  2015, Knowledge Resources and partner company Three Byte Intermedia (TBI) present a subset of the MoMath Robot swarm on the tip of the Xilinx booth at EW15.

The exhibit demonstrates the image processing capabilities of the robots Xilinx Zynq core. Visitors were impressed by the responiseveness of the absolute coordinate system tracking method and the smooth, seemingly natural behavior of the robots which emerged from the swarm algorithms and collision avoidance system of TBI.

KR & TBI at xilinx booth of EW15

KR & TBI at xilinx booth of EW15

Posted in Events, News

Robot Swarm at MoMath in NYC completed

December 2014, Knowledge Resources developed and built the robots that are the heart of the physical installation of the soon to open robot swarm exhibit of the Museum of Mathematics in New York City (MoMath). The robots feature a novel optical tracking system that allows each of them to be “aware” of their position and orientation with sub mm accuracy. The tracking systems image analysis is implemented in VHDL and mapped into the fabric of a Xilinx SoC on Knowledge Resources KRM3Z20 Module. Technical imformation is available by contacting Knowledge Resources, a more entertaining view is presented by this New York Times article.

Further Press coverage of the exhibit:

NY1 Morning show



Academic announcements:

Rice University

Partner Blogs:

Three Byte Intermedia

New Project

Posted in News

NEW Website and corporate Logo

October 2013, after 9 years, it was decided to update the appearance of our website which includes our new logo. Our new features include opinions, updated projects, a customer portal to our new online project management system and a web shop, which will be available shortly.

Posted in News

The first FOM7050 compliant Zynq modules are here

September 2013:  Our KRM-3Z20-512 FPGA module is the first member in a growing family of standardized modules that are FOM7050 compliant.  With 192 FPGA I/O’s and a fully accessible MIO1 Bank, this modules offers the utmost design flexibility as no pins are wasted on potentially unused special purpose I/O signals.

The modules are supported by a development board which offers Gigabit Ethernet, USB, micro SD, UART to USB, four expansion ports, two logic analyzer ports, user buttons and LED’s and (much) more. A range of special purpose I/O modules can be used to quickly assemble a complete prototyping system.

Modules in single quantities cost only € 198.00  and the evaluation carrier boards € 149.00.

Pre-orders are now being accepted  and the expected ship date is in the second half of October.

For more detailed information, data-sheet, and access to library information please send an email with your contact information to



Posted in News

The “Perfect” FPGA Module (Part 2)

SO, since our first attempt of creating the “perfect” FPGA module was quite successful, we decided to try and do even better.  Not that the KRM1k modules don’t have their place, but time (and therefore technology) progresses and the features that are now available in the 7 series parts from Xilinx could simply not be encapsulated in a SO-DIMM form factor module and at the same time be fully accessible by the system designer.

I quickly re-iterate the original two driving rules for a Knowledge Resources FPGA module design:

the modules only carry features that are required in every design.

  • Core power supply
  • Configuration memory
  • Reset and proper initialization

features are also included if they add significant complexity to the design if they had to be implemented on the carrier.

  • DDR memories
  • Use of small pitch & high I/O count FPGA packaging

Sticking to those rules has served us well with the KRM1K module but we feel that there is always room for improvement so we are adding the following rules before starting the design of the next generation:

Rule #3

… A module may not limit access to key features of an FPGA family

  • MGT’s must be accessible
  • Processing subsystem pins must be accessible

Rule #4

… I/O signals on a module connector must be as universally usable as possible

  • Bank voltages must be flexible and decided by the end use design not the module
  • Signals must be length matched between FPGA and carrier board interconnect to allow for fast buses
  • Signals should be available on “board down” connectors and not via extra flex cables whenever possible

Rule #5

… Modules should provide a fully compatible upgrade path between FPGA members and families

  • Byte groups (T0-T3) must be mapped consistently on all module variants
  • A Kintex module variant must be able to provide MIO features of a Zynq variant via soft cores
  • Dedicated MGT lanes must be reserved
  • A common heat management specification, with consistent build envelope, must exist

In defining the KRM3k specification, we listed to our own wishes, and why not?   

KRM3k modules feature the following common external features:

  • 70mm x 50mm , 5mm or 4mm spacing to carrier (connector choice in end-user design)
  • Heat spreader for a total build height of 10mm or 11mm (depending on connector choice)
  • 4×48 bit PL GPIO (192 GPIO signals, 96 diff pairs)
  • the entire MIO_1 signal range
  • up to 8 MGT lanes with 2 MGT ref-clock inputs
  • JTAG
  • Config done OC output
  • Reset input

The first product that is based on this specification is the KRM-3Z20-512 board. It features:

  • Xilinx Zynq XC7Z020-1CLG484C
  • 2 Instances of 128Mb x16 LP DDRIII RAM @667MHz (512MB total)
  • 256Mb config memory, two times 4X SPI memory
  • 4 application status LED

I think we did it… it is perfect (at least until we come up with something even better..)  ;-)

Posted in Our Thinking

The “Perfect” FPGA Module (Part 1)

OK, I admit there is no such thing as a “perfect” FPGA module, but one should at least try to come as close as possible. So when we, at Knowledge Resources, contemplated the use of pre-built FPGA modules in order to accelerate the development of some simpler small run projects, we looked at commercially available offerings and found them to be interesting but never quite right for our needs. In addition to imperfect fit, they were also rather expensive, at least when considered in small quantities. So we started our own module design in the spring of 2012. Here are the thoughts that drove the shape and features of our first module family, the KRM1k.:

  • It needs to be as universally useable as possible, therefore we were aiming for as many generic I/O’s as possible and tried to avoid special purpose I/O’s such as dedicated USB, ethernet or video.
  • It needs to significantly simplify the design of the carrier board. Simplification comes in two forms:
    • Fewer layers are required compared to a design that has the FPGA BGA package directly on the main PCB
    • The PCB trace & spacing geometries can be relaxed
  • It needs to be low cost enough so that it is a viable commercial option for applications ranging from quick projects, educational kits and small to medium volume products.
  • Spare FPGA pins that cannot be exposed as module I/O’s (due to the modules pin constraints) may be used to implement “nice to have” features on the module as long as they do not add significant cost to the final module. Examples include logic analyzer test points, (which come for free if implemented for connectorless probes) or status LED’s or maybe a micro SD connector for more local storage…all nice to have and less than 1% impact on the modules BOM.

It turns out that the universal usability is a key feature and a big distinguishing aspect of Knowledge Resources modules from the competitors offerings. In order to being universal, the first design rule is that…

the modules only carry  features that are required in every design.

  • Core power supply
  • Configuration memory
  • Reset and proper initialization

This first rule is broken slightly by adding features that are highly likely to be needed and would…

add significant complexity to the design if they had to be implemented on the carrier.

  • DDR memories
  • Use of small pitch & high I/O count FPGA packaging

For our first design, we chose the Xilinx Spartan6 LX75 in the GFF676 packaging because it offers the largest Spartan 6 FPGA that is still supported by the free ISE web-pack (we considered that important for hobbyist and educational clients) but offers a reasonably large amount of logic and multiple hard IP memory controllers, has a pin-compatible upgrade path (LX 100 & LX150) and a downgrade path (LX45). The SO-DIMM form factor choice was largely driven by the low cost of the mating connector and the connector-less aspect of the module (also a cost consideration). In hindsight, this was not well considered since the 200 pins available on a SO-DIMM header turn out to be a severe I/O constraint if one designs the module with ample GND and power pins so that even  designs that need to bring faster signals into or out of the module, have a chance of functioning properly. Since, even after implementing two separate instances of DDR III Memory, we had so many unused pins on the FPGA, we added two 50 pin Ziff connector expansion ports. Each of the ports expose 32 GP I/O’s, and 2 clock pairs, provide ample GND and 3.3V supply to the expansion module.

The end result is our KRM-1075-512-x, a pretty useful, nearly perfect module that we have used in several projects and countless “quick experiments” . It may not be perfect, but it sure does come close ;-)



Posted in Featured, Our Thinking

Second Year of Certified Xilinx Alliance Partner Status

March 2013  We are proud to announce the achievement of certified Xilinx Alliance partner for the second year in a row.  Our growing team of certified Xilinx developers are looking forward to serving our mutual client base with expertise and dedication.

Posted in News